Technical Field
The embodiments disclosed within relate to integrated circuits, and more particularly, to the operation of multi-core processors.
Description of the Related Art
Processors are used in a variety of applications ranging from desktop computers to cellular telephones. In some applications, multiple processors or processor cores may be connected together so that computation tasks may be shared among the various processors. Whether used individually, or as part of group, processors make use of sequential logic circuits, internal memory, registers, state machines and the like, to execute program instructions and operate on input data.
Modern processors typically include various functional blocks, each with a dedicated task. For example, a processor may include an instruction fetch unit, a memory management unit, and an arithmetic logic unit (ALU). An instruction fetch unit may prepare program instructions for execution by decoding the program instructions and checking for scheduling hazards. Arithmetic operations such as addition, subtraction, multiplication, and division as well as and Boolean operations (e.g., AND, OR, etc.) may be performed by an ALU. Some processors include high-speed memory (commonly referred to as “cache memories” or “caches”) used for storing frequently used instructions or data.
With various functional blocks operating on, exchanging, and calculating various groups of data, potential exist for problems to occur within a processor. During operation, a processor core may enter a state from which it cannot continue executing instructions. A core may enter such an inoperable state for a variety of reasons, including reading data from an uninitialized memory location, waiting for data in a memory location to change, waiting for a response from an idle or unresponsive peripheral device or coprocessor, a glitch occurring on a clock or other input signal that causes only a portion of the core's logic to react, physical damage to a circuit element in the core, etc.
Once a core enters an inoperable or “stalled” state, the core may require a reset to exit the stalled state and restart execution of a software process it that was previously executing, resulting in a loss of processing time and potentially delaying other processor cores waiting on output from the inoperable core. In other embodiments, the core may need to be powered off and then powered back on to exit the stalled state. Sometimes referred to as “power cycling,” this may result in a greater loss of processing time potentially causing greater delays as other cores in the processor being power cycled may also have to restart execution of their respective software processes. In some embodiments, particularly if physical damage either cased or resulted from the inoperable core, then a system including the core may be disabled and replaced, which could result in an extended period of “downtime” in which the system is unusable.